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S6C1652
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
August. 1999. Ver. 0.0
Prepared by:
Dae-Young, Ahn
Mail: jesus9@samsung.co.kr
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
S6C1652
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C1652 Specification Revision History Version 0.0 Original Content Date Aug.1999
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6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C1652
CONTENTS
INTRODUCTION ................................................................................................................................................. 4 FEATURES ......................................................................................................................................................... 4 BLOCK DIAGRAM .............................................................................................................................................. 5 PIN ASSIGNMENTS............................................................................................................................................ 6 PIN DESCRIPTIONS........................................................................................................................................... 7 OPERATION DESCRIPTION .............................................................................................................................. 8 DISPLAY DATA TRANSFER............................................................................................................................ 8 EXTENSION OF OUTPUT ............................................................................................................................... 8 RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE................................................. 8 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 15 RECOMMENDED OPERATION CONDITIONS ................................................................................................. 15 DC CHARACTERISTICS................................................................................................................................... 16 AC CHARACTERISTICS................................................................................................................................... 17 WAVEFORMS ................................................................................................................................................... 18 RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD....................... 19
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S6C1652
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
INTRODUCTION
The S6C1652 is a 300 / 309 channel output, TFT-LCD source driver for an 64 gray-scale LCD panel. Data input is based on digital input consisting of 6 bits by 3 dots, which can realize a full-color display of 260,000 color by output of 64 values gamma-corrected. This device has an internal D/A (digital-to-analog) converter for each output and 18 (9-by-2) reference voltages. Because the output dynamic range is as large as 6.0 - 12.6 Vp-p, it is unnecessary to operate level inversion of the LCD's common electrode. Besides, to be able to deal with dot-line inversion when mounted on a single-side, output gray-scale voltages with different polarity can be output to the odd number output pins and the even output pins. S6C1652 can be adopted to larger panel, and SHL (shift direction selection) pin makes the use of the LCD panel connection conveniently. Maximum operation clock frequency is 55 MHz at 2.7 V logic operation, single edge and it can be applied to the TFT-LCD panel of SVGA to XGA standard.
FEATURES
* * * * * * * * * * * * TFT active matrix LCD source driver LSI 64 gray-scale is possible through 18 (9-by-2) reference voltages and D/A converter Dot inversion display is possible CMOS level input Compatible with gamma-correction Input of 6bits (gray-scale data) by 3 dots (R,G,B) Logic supply voltage: 2.7 - 3.6 V LCD driver supply voltage: 6.4 - 13.0 V Output dynamic range: 6.0 - 12.6 Vp-p Maximum operating frequency: fMAX = 55 MHz (internal data transmission rate at 2.7 V operation) Output: 300 / 309 outputs TCP available
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6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C1652
BLOCK DIAGRAM
Y309
Y308
Y307
Y003
BIAS
Output Buffer
TESTB
POL VGMA1 VGMA18
18
D/A Converter
6
6
6
6
6
Y002 6 6
6
CLK1
Data Latch
6
6
6
6
6
Data Register
6 D00 - D05 D10 - D15 D20 - D25 6 6 6 Data Control 18
6
6
6
6
103bit Shift Register
CLK2
DIO2
SHL
DIO1
Figure 1. S6C1652 Block Diagram
Y001
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S6C1652
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
PIN ASSIGNMENTS
Y001 Y002 Y003 Y004
VSS2 VDD2 VSS1 D05 D04 D03 D02 D01 D00 D15 D14 D13 D12 D11 D10 DIO1 VGMA1 VGMA2 VGMA3 VGMA4 VGMA5 VGMA6 VGMA7 VGMA8 VGMA9 VGMA10 VGMA11 VGMA12 VGMA13 VGMA14 VGMA15 VGMA16 VGMA17 VGMA18 SELT CLK2 DIO2 CLK1 POL D25 D24 D23 D22 D21 D20 SHL TESTB VDD1 VDD2 VSS2
S6C1652
Y306 Y307 Y308 Y309
Figure 2. S6C1652 Pin Assignments
6
(Top View)
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C1652
PIN DESCRIPTIONS
Symbol VDD1 VDD2 VSS1 VSS2 Y1 - Y309 D0<0:5> - D2<0:5> Pin Name Logic power supply Driver power supply Logic ground Driver ground Driver outputs Display data input 2.7 - 3.6 V 6.4 - 13.0 V Ground (0 V) Ground (0 V) The D/A converted 64 gray-scale analog voltage is output. The display data is input with a width of 18 bits, gray-scale data (6 bits) by 3 dots (R,G,B) DX0: LSB, DX5: MSB Description
SHL
This pin controls the direction of shift register in cascade connection. The shift direction of the shift registers is as follows. Shift direction control input SHL = H: DIO1 input, Y1 Y309, DIO2 output SHL = L: DIO2 input, Y309 Y1, DIO1 output Start pulse input / output Start pulse input / output SHL = H: Used as the start pulse input pin SHL = L: Used as the start pulse output pin SHL = H: Used as the start pulse output pin SHL = L: Used as the start pulse input pin POL = H: The reference voltage for odd number outputs are VGMA1 - VGMA9 and those for even number outputs are VGMA10 - VGMA18 POL = L: The reference voltage for odd number outputs are VGMA10 - VGMA18 and those for even number outputs are VGMA1 - VGMA9 Refer to the shift register's shift clock input. The display data is loaded to the data register at the rising edge of CLK2. Latches the contents of the data register at rising edge and transfers them to the D/A converter. Also, after CLK1 input, clears the internal shift register contents. After 1 pulse input on start, operates normally. CLK1 input timing refers to the "Relationships between CLK1 start pulse (DIO1, DIO2) and blanking period" of the switching characteristic waveform. Outputs the gray-scale data at rising edge. Input the gamma corrected power supplies from external source. VDD2 > VGMA1 > VGMA2 > ......... > VGMA17 > VGMA18 > VSS2 Keep gray-scale power supply unchanged during the gray-scale voltage output. SELT = H: 300 Output (Y151 - Y159 are disabled) SELT = L: 309 Output TESTB = H: Normal operation mode TESTB = L: Test mode (OP AMP CUT-OFF, Rpu = 30k)
DIO1 DIO2
POL
Polarity input
CLK2
Shift clock input
CLK1
Latch input
VGMA1 - VGMA18 SELT TESTB
Gamma corrected power supplies
Output selection input Test input
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S6C1652
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
OPERATION DESCRIPTION
DISPLAY DATA TRANSFER
When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse enables the data transfer operation. After the falling edge of DIO1 (or DIO2), display data is valid on the rising edge of CLK2. Once all the data of 300 / 309 channels are loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is provided, new display data is valid on the next rising edge of CLK2 after the falling edge of DIO1 (or DIO2).
EXTENSION OF OUTPUT
Output pin can be adjusted to an extended screen by cascade connection. (1) SHL = "L" Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins except DIO1 and DIO2 are connected together in each device. (2) SHL = "H" Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins except DIO2 and DIO1 are connected together in each device.
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE
The LCD drive output voltages are determined by the input data and 18 (9-by-2) gamma corrected power supplies (VGMA1 - VGMA18). Besides, to be able to deal with dot-line inversion when mounted on a singleside, gradation voltages with different polarity can be output to the odd number output pins and the even number output pins. Among 9-by-2 gamma corrected voltages, input gray-scale voltages of the same polarity with respect to the common voltage, for the respective 9 gamma corrected voltages of VGMA1 - VGMA9 and VGMA10 - VGMA18.
SHL = H
OUTPUT DATA D00 - D05 Y1 Y2 First D10 - D15 D20 - D25 ...... D00 - D05 Y3 ...... Y307 Y308 Last D10 - D15 D20 - D25 Y309
SHL = L
OUTPUT DATA D00 - D05 Y1 Y2 Last D10 - D15 D20 - D25 ...... D00 - D05 Y3 ...... Y307 Y308 First D10 - D15 D20 - D25 Y309
Figure 3. Relationship between Shift Direction and Output Data
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6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C1652
VDD2 VGMA1 VGMA2 VGMA3 VGMA4 VGMA5 VGMA6 VGMA7 VGMA8 VGMA9 VGMA10 VGMA11 VGMA12 VGMA13 VGMA14 VGMA15 VGMA16 VGMA17 VGMA18 VSS2 00H 08H 10H 18H 20H 28H 30H 38H 3FH Input data
VCOM
Figure 4. Gamma Correction Curve
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S6C1652
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
Table 1. Resistor Strings (R0 - R63, unit: ) Name R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Value 510 510 510 510 510 510 510 510 255 255 255 255 255 255 255 255 Name R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 Value 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 Name R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 Value 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 Name R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 Value 255 255 255 255 255 255 255 255 510 510 510 510 510 510 510 510
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6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C1652
Table 2. Relationship between Input Data and Output Voltage Value Input data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH DX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 G/S VH0 VH1 VH2 VH3 VH4 VH5 VH6 VH7 VH8 VH9 VH10 VH11 VH12 VH13 VH14 VH15 VH16 VH17 VH18 VH19 VH20 VH21 VH22 VH23 VH24 VH25 VH26 VH27 VH28 VH29 VH30 VH31 Output voltage VGMA1 VGMA1 + (VGMA2 - VGMA1) x 1 / 8 VGMA1 + (VGMA2 - VGMA1) x 2 / 8 VGMA1 + (VGMA2 - VGMA1) x 3 / 8 VGMA1 + (VGMA2 - VGMA1) x 4 / 8 VGMA1 + (VGMA2 - VGMA1) x 5 / 8 VGMA1 + (VGMA2 - VGMA1) x 6 / 8 VGMA1 + (VGMA2 - VGMA1) x 7 / 8 VGMA2 VGMA2 + (VGMA3 - VGMA2) x 1 / 8 VGMA2 + (VGMA3 - VGMA2) x 2 / 8 VGMA2 + (VGMA3 - VGMA2) x 3 / 8 VGMA2 + (VGMA3 - VGMA2) x 4 / 8 VGMA2 + (VGMA3 - VGMA2) x 5 / 8 VGMA2 + (VGMA3 - VGMA2) x 6 / 8 VGMA2 + (VGMA3 - VGMA2) x 7 / 8 VGMA3 VGMA3 + (VGMA4 - VGMA3) x 1 / 8 VGMA3 + (VGMA4 - VGMA3) x 2 / 8 VGMA3 + (VGMA4 - VGMA3) x 3 / 8 VGMA3 + (VGMA4 - VGMA3) x 4 / 8 VGMA3 + (VGMA4 - VGMA3) x 5 / 8 VGMA3 + (VGMA4 - VGMA3) x 6 / 8 VGMA3 + (VGMA4 - VGMA3) x 7 / 8 VGMA4 VGMA4 + (VGMA5 - VGMA4) x 1 / 8 VGMA4 + (VGMA5 - VGMA4) x 2 / 8 VGMA4 + (VGMA5 - VGMA4) x 3 / 8 VGMA4 + (VGMA5 - VGMA4) x 4 / 8 VGMA4 + (VGMA5 - VGMA4) x 5 / 8 VGMA4 + (VGMA5 - VGMA4) x 6 / 8 VGMA4 + (VGMA5 - VGMA4) x 7 / 8
NOTE: VDD2>VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8>VGMA9
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S6C1652
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input data 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 G/S VH32 VH33 VH34 VH35 VH36 VH37 VH38 VH39 VH40 VH41 VH42 VH43 VH44 VH45 VH46 VH47 VH48 VH49 VH50 VH51 VH52 VH53 VH54 VH55 VH56 VH57 VH58 VH59 VH60 VH61 VH62 VH63 Output voltage VGMA5 VGMA5 + (VGMA6 - VGMA5) x 1 / 8 VGMA5 + (VGMA6 - VGMA5) x 2 / 8 VGMA5 + (VGMA6 - VGMA5) x 3 / 8 VGMA5 + (VGMA6 - VGMA5) x 4 / 8 VGMA5 + (VGMA6 - VGMA5) x 5 / 8 VGMA5 + (VGMA6 - VGMA5) x 6 / 8 VGMA5 + (VGMA6 - VGMA5) x 7 / 8 VGMA6 VGMA6 + (VGMA7 - VGMA6) x 1 / 8 VGMA6 + (VGMA7 - VGMA6) x 2 / 8 VGMA6 + (VGMA7 - VGMA6) x 3 / 8 VGMA6 + (VGMA7 - VGMA6) x 4 / 8 VGMA6 + (VGMA7 - VGMA6) x 5 / 8 VGMA6 + (VGMA7 - VGMA6) x 6 / 8 VGMA6 + (VGMA7 - VGMA6) x 7 / 8 VGMA7 VGMA7 + (VGMA8 - VGMA7) x 1 / 8 VGMA7 + (VGMA8 - VGMA7) x 2 / 8 VGMA7 + (VGMA8 - VGMA7) x 3 / 8 VGMA7 + (VGMA8 - VGMA7) x 4 / 8 VGMA7 + (VGMA8 - VGMA7) x 5 / 8 VGMA7 + (VGMA8 - VGMA7) x 6 / 8 VGMA7 + (VGMA8 - VGMA7) x 7 / 8 VGMA8 VGMA8 + (VGMA9 - VGMA8) x 1 / 8 VGMA8 + (VGMA9 - VGMA8) x 2 / 8 VGMA8 + (VGMA9 - VGMA8) x 3 / 8 VGMA8 + (VGMA9 - VGMA8) x 4 / 8 VGMA8 + (VGMA9 - VGMA8) x 5 / 8 VGMA8 + (VGMA9 - VGMA8) x 6 / 8 VGMA8 + (VGMA9 - VGMA8) x 7 / 8
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6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C1652
Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH DX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 G/S VL0 VL1 VL2 VL3 VL4 VL5 VL6 VL7 VL8 VL9 VL10 VL11 VL12 VL13 VL14 VL15 VL16 VL17 VL18 VL19 VL20 VL21 VL22 VL23 VL24 VL25 VL26 VL27 VL28 VL29 VL30 VL31 Output voltage VGMA18 VGMA18 + (VGMA17 - VGMA18) x 1 / 8 VGMA18 + (VGMA17 - VGMA18) x 2 / 8 VGMA18 + (VGMA17 - VGMA18) x 3 / 8 VGMA18 + (VGMA17 - VGMA18) x 4 / 8 VGMA18 + (VGMA17 - VGMA18) x 5 / 8 VGMA18 + (VGMA17 - VGMA18) x 6 / 8 VGMA18 + (VGMA17 - VGMA18) x 7 / 8 VGMA17 VGMA17 + (VGMA16 - VGMA17) x 1 / 8 VGMA17 + (VGMA16 - VGMA17) x 2 / 8 VGMA17 + (VGMA16 - VGMA17) x 3 / 8 VGMA17 + (VGMA16 - VGMA17) x 4 / 8 VGMA17 + (VGMA16 - VGMA17) x 5 / 8 VGMA17 + (VGMA16 - VGMA17) x 6 / 8 VGMA17 + (VGMA16 - VGMA17) x 7 / 8 VGMA16 VGMA16 + (VGMA15 - VGMA16) x 1 / 8 VGMA16 + (VGMA15 - VGMA16) x 2 / 8 VGMA16 + (VGMA15 - VGMA16) x 3 / 8 VGMA16 + (VGMA15 - VGMA16) x 4 / 8 VGMA16 + (VGMA15 - VGMA16) x 5 / 8 VGMA16 + (VGMA15 - VGMA16) x 6 / 8 VGMA16 + (VGMA15 - VGMA16) x 7 / 8 VGMA15 VGMA15 + (VGMA14 - VGMA15) x 1 / 8 VGMA15 + (VGMA14 - VGMA15) x 2 / 8 VGMA15 + (VGMA14 - VGMA15) x 3 / 8 VGMA15 + (VGMA14 - VGMA15) x 4 / 8 VGMA15 + (VGMA14 - VGMA15) x 5 / 8 VGMA15 + (VGMA14 - VGMA15) x 6 / 8 VGMA15 + (VGMA14 - VGMA15) x 7 / 8
NOTE: VGMA10>VGMA11>VGMA12>VGMA13>VGMA14>VGMA15>VGMA16>VGMA17>VGMA18>VSS2
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S6C1652
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input data 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 G/S VL32 VL33 VL34 VL35 VL36 VL37 VL38 VL39 VL40 VL41 VL42 VL43 VL44 VL45 VL46 VL47 VL48 VL49 VL50 VL51 VL52 VL53 VL54 VL55 VL56 VL57 VL58 VL59 VL60 VL61 VL62 VL63 Output voltage VGMA14 VGMA14 + (VGMA13 - VGMA14) x 1 / 8 VGMA14 + (VGMA13 - VGMA14) x 2 / 8 VGMA14 + (VGMA13 - VGMA14) x 3 / 8 VGMA14 + (VGMA13 - VGMA14) x 4 / 8 VGMA14 + (VGMA13 - VGMA14) x 5 / 8 VGMA14 + (VGMA13 - VGMA14) x 6 / 8 VGMA14 + (VGMA13 - VGMA14) x 7 / 8 VGMA13 VGMA13 + (VGMA12 - VGMA13) x 1 / 8 VGMA13 + (VGMA12 - VGMA13) x 2 / 8 VGMA13 + (VGMA12 - VGMA13) x 3 / 8 VGMA13 + (VGMA12 - VGMA13) x 4 / 8 VGMA13 + (VGMA12 - VGMA13) x 5 / 8 VGMA13 + (VGMA12 - VGMA13) x 6 / 8 VGMA13 + (VGMA12 - VGMA13) x 7 / 8 VGMA12 VGMA12 + (VGMA11 - VGMA12) x 1 / 8 VGMA12 + (VGMA11 - VGMA12) x 2 / 8 VGMA12 + (VGMA11 - VGMA12) x 3 / 8 VGMA12 + (VGMA11 - VGMA12) x 4 / 8 VGMA12 + (VGMA11 - VGMA12) x 5 / 8 VGMA12 + (VGMA11 - VGMA12) x 6 / 8 VGMA12 + (VGMA11 - VGMA12) x 7 / 8 VGMA11 VGMA11 + (VGMA10 - VGMA11) x 1 / 8 VGMA11 + (VGMA10 - VGMA11) x 2 / 8 VGMA11 + (VGMA10 - VGMA11) x 3 / 8 VGMA11 + (VGMA10 - VGMA11) x 4 / 8 VGMA11 + (VGMA10 - VGMA11) x 5 / 8 VGMA11 + (VGMA10 - VGMA11) x 6 / 8 VGMA11 + (VGMA10 - VGMA11) x 7 / 8
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6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C1652
ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V) Parameter Logic supply voltage Driver supply voltage Input voltage Output voltage Operating power dissipation Operation temperature Storage temperature Symbol VDD1 VDD2 VGMA1 - 18 Others DIO1, 2 Y1 - Y309 Pd Top Tstg Ratings -0.3 to 6.5 -0.3 to 15.0 -0.3 to VDD2 + 0.3 -0.3 to VDD1 + 0.3 -0.3 to VDD1 + 0.3 -0.3 to VDD2 + 0.3 150 (1) -20 to 75 -55 to 125 Unit V V V V mW C C
NOTE: Relationship between TFT-LCD panel and Pd (Pd CL* (VDD2)2 * fCLK1)
CAUTIONS: If LSIs are stressed beyond those listed above "absolute maximum ratings", they may be permanently destroyed. These are stress ratings only, and functional operation of the device at these or any other condition beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Turn on power order: VDD1 control signal input VDD2 VGMA1 - VGMA18 Turn off power order: VGMA1 - VGMA18 VDD2 control signal input VDD1
RECOMMENDED OPERATION CONDITIONS
Table 4. Recommended Operation Conditions (Ta = -20 to 75 C, VSS1 = VSS2 = 0 V) Parameter Logic supply voltage Driver supply voltage Gamma corrected voltage Driver part output voltage Maximum clock frequency Output load capacitance Symbol VDD1 VDD2
(1)
Min. 2.7 6.4 0.5VDD2 VSS2 + 0.2 VSS2 + 0.2
Typ. 3.0 9.0 -
Max. 3.6 13.0 VDD2 - 0.2 0.5VDD2 VDD2 - 0.2 55 150
Unit V V V V V MHz pF / PIN
VGMA1 - VGMA9 VGMA10 - VGMA18 Vyo fmax CL
(1)
VDD1 = 2.7 V -
NOTE: Relationship between TFT-LCD panel and Pd (Pd CL* (VDD2)2 * fCLK1)
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S6C1652
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
DC CHARACTERISTICS
Table 5. DC Characteristics (Ta = -20 to 75 C, VDD1 = 2.7 to 3.6 V, VDD2 = 6.4 to 13.0 V, VSS1 = VSS2 = 0V) Parameter Symbol Condition Min. Typ. Max. Unit High level input voltage Low level input voltage Input leakage current High level output voltage Low level output voltage Resistor VIH VIL IL VOH VOL R0 - R63 IVOH Driver output current IVOL Output voltage deviation Output voltage range Logic part dynamic current Driver part dynamic current VO Vyo IDD1 IDD2 SHL, CLK2, D00 - D25, CLK1, SELT, POL, DIO1 (DIO2) DIO1 (DIO2), IO = -1.0 mA DIO1 (DIO2), IO = +1.0 mA Refer to Table 1. Resistor Strings VDD2 = 9.0 V, Vx = 2.5 V, Vyo = 8.5 V(1) VDD2 = 9.0 V, Vx = 6.5 V, Vyo = 0.5 V(1) Input data: 00H to 3FH Input data: 00H to 3FH VDD1 = 3.0 V (2) VDD1 = 3.0 V, VDD2 = 9.0 V
(2)(3)(4)
0.75VDD1 0 -1 VDD1 - 0.5 Rn x 0.7 0.5 VSS2 + 0.2 -
-1.0 1.0 8 2.0 5.0
VDD1 0.25VDD1 1 0.5 Rn x 1.3 -0.5 15 VDD2 - 0.2 3.5
V A V mA mA mV V
mA 7.0
NOTES: 1. Vyo is the output voltage of analog output pins Y1 to Y309. Vx is the voltage applied to analog output pins Y1 to Y309. 2. CLK1 period is defined to be 20 s at fCLK2 = 33 MHz, data pattern = 101010(checkerboard pattern), Ta = 25 C. 3. The current consumption per driver when XGA single-sided mounting (10 drivers) is connected in cascade 4. Yout Load Condition
YOUT
5k
10k
10k
25pF VCOM = 0.5VDD2 5k 10k
25pF 10k
25pF
Figure 5. Yout Load Condition
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6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C1652
AC CHARACTERISTICS
Table 6. AC Characteristics (Ta = -20 to 75 C, VDD1 = 2.7 to 3.6 V, VDD2 = 6.4 to 13.0 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition Min. Typ. Max. Clock pulse width Clock pulse low period Clock pulse high period Data setup time Data hold time Start pulse setup time Start pulse hold time Start pulse delay time CLK1 - DIO (input) setup time CLK1 pulse high period Driver output delay time1 Driver output delay time2 Data invalid period Last data timing CLK1 - CLK2 time POL - CLK1 time PWCLK PWCLK (L) PWCLK (H) tSETUP1 tHOLD1 tSETUP2 tHOLD2 tPLH1 tSETUP3 PWCLK1 tPHL1 tPHL2 tINV tLDT tCLK1 - CLK2 tPOL - CLK1
(1) (2)
Unit
CL = 20pF Refer to Figure 5 Refer to Figure 5 DIO1 (2) CLK2 CLK1 CLK2 POLor CLK1
18 4 4 4 0 4 0 1 3 1 6 -9
1 -
12 5 10 CLK2 period s CLK2 period ns ns ns
NOTES: 1. The value is specified when the drive voltage value reaches the target output voltage level of 90% 2. The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.
17
18
PWCLK tINV 1st tSETUP1 tHOLD1 INVALID DATA tHOLD2 tSETUP2 1st DATA VIH VIL LAST-1 LAST PWCLK (L) PWCLK (H) tPLH1 tSETUP3 PWCLK1 tPHL1 Target output voltage 90% Target output voltage tPHL2 tLDT tCLK1 - CLK2 0.5VDD1 LAST DATA tPOL - CLK1 INVALID DATA
S6C1652
CLK2
DXX
DIO1 input (DIO2 input)
DIO2 output (DIO1 output)
WAVEFORMS (VIH = 0.75VDD1, VIL = 0.25VDD1)
CLK1
Figure 6. Waveforms
Y(1:309)
CLK2
CLK1
DXX
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
POL
CLK2
DIO1 input (DIO2 input)
0.5VDD1 1CLK2 1CLK2 (Min.) tLDT Nth DATA INVALID DATA blanking time = Min. 3CLK2 First data in the next line 1st DATA 2nd DATA
CLK1
DXX
N-1th DATA
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
Last data
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD
Figure 7. Waveforms
VGMA10 - VGMA18 VGMA1 - VGMA9 VGMA10 - VGMA18 VGMA1 - VGMA9 VGMA10 - VGMA18 VGMA1 - VGMA9
CLK1
POL
Y2N-1: odd number output
Y2N: even number output
S6C1652
19

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